Plug-in memories having batteries effective when unplugged are known, as described, for example, in IBM Technical Disclosure Bulletin articles entitled "Pluggable Storage Modules," by Atkinson et al, Vol. 15, No. 11, April 1973, at pp. 3408-3409, and "Volatile Memory Data Retention," by Anderson et al, Vol. 14, No. 9, February 1972, at pp. 2712-2713, and in U.S. Pat. Nos. 4,229,804 to Kobayashi et al and 4,383,184 to McFarland and United Kingdom Patent Specification No. 1,554,013 to Ferranti Limited, published Oct. 17, 1979.
Such prior art is not known to include circuitry operating upon the terminals to memory to protect the memory content. The United Kingdom Patent specification discloses low impedance paths to prevent build-up of static electricity to all terminals of a plug-in memory, which in no way provides a control signal to the memory which might protect data.
U.S. Pat. No. 4,485,456 to Toyoda is to preserving information in a memory which is part of a fixed data processing system having input terminals to the system. Reserve power is provided to the memory and to a latch or logic which applies a write inhibit signal to the memory. A signal to one of the system input terminals is one control signal to that latch or logic.
U.S. Pat. No. 4,445,198 to Eckert is not to a plug-in memory nor to a system having a reserve battery. It addresses a specialized problem of a microprocessor writing incorrect data into an associated memory at low voltage levels occurring during loss of power. To counter this, a voltage input to the memory required to permit writing, which is normally always provided at normal power, is replaced by a voltage of opposite polarity as power is lost.